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Silicon Labs /BGM210P032JIA /USART1_NS /CTRLX

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Interpret as CTRLX

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DISABLE)DBGHALT 0 (DISABLE)CTSINV 0 (DISABLE)CTSEN 0 (DISABLE)RTSINV 0 (RXPRSEN)RXPRSEN 0 (CLKPRSEN)CLKPRSEN

RTSINV=DISABLE, DBGHALT=DISABLE, CTSEN=DISABLE, CTSINV=DISABLE

Description

No Description

Fields

DBGHALT

Debug halt

0 (DISABLE): Continue to transmit until TX buffer is empty

1 (ENABLE): Negate RTS to stop link partner’s transmission during debug HALT. NOTE** The core clock should be equal to or faster than the peripheral clock; otherwise, each single step could transmit multiple frames instead of just transmitting one frame.
CTSINV

CTS Pin Inversion

0 (DISABLE): The USn_CTS pin is low true

1 (ENABLE): The USn_CTS pin is high true
CTSEN

CTS Function enabled

0 (DISABLE): Ingore CTS

1 (ENABLE): Stop transmitting when CTS is negated
RTSINV

RTS Pin Inversion

0 (DISABLE): The USn_RTS pin is low true

1 (ENABLE): The USn_RTS pin is high true
RXPRSEN

PRS RX Enable
CLKPRSEN

PRS CLK Enable

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data